Abstract
This blog traces the curious silence surrounding India’s semiconductor-specific IP regime at a time when chips sit at the centre of geopolitics, AI, and digital sovereignty. It explores how the Semiconductor Integrated Circuits Layout-Design (SICLD) Act, 2000 emerged from global concerns around “chip piracy” and TRIPS compliance, yet gradually slipped into obscurity despite India’s growing semiconductor ambitions. Moving beyond black-letter law, the piece examines what this dormancy reveals about India’s approach to technology governance: fragmented institutions, compliance-driven lawmaking, and the marginalisation of niche IP subjects.
Introduction
Every conversation about semiconductors today quickly spirals into geopolitics, AI, and digital sovereignty. The race for AI accelerators has turned Graphics Processing Unit (GPUs) and custom Application-Specific Integrated Circuits (ASICs) into strategic assets and governments now talk about fabrication facilities with the same seriousness they once reserved for oil fields.
India has stepped firmly into this conversation through the ₹76,000‑crore Semicon India Programme, design‑linked incentives for fabless companies, and a flurry of announcements on chip design centres, packaging units, and AI hardware R&D.
Against this backdrop, it feels almost paradoxical that India already has a dedicated statute, The Semiconductor Integrated Circuits Layout‑Design Act, 2000 (SICLD Act) that barely features in mainstream IP or tech‑policy discussions.
Across the last two decades, scholars and practitioners have repeatedly described the law as underutilised and under‑enforced. The core claim of this blog is simple: India’s semiconductor‑specific IP regime has remained dormant, under‑discussed, under‑litigated, and largely disconnected from semiconductor policy conversations, even as chips and AI hardware have become central to India’s economic and strategic ambitions.
Why a Separate Semiconductor IP Regime Was Created
To understand why this statute exists at all, we need to understand the technology it protects.
A chip’s layout‑design (or mask work/topography) is the three‑dimensional blueprint of how transistors, interconnects, and other elements are arranged on silicon to perform electronic functions. These layouts embody significant engineering judgment, optimisation work, and capital‑intensive design effort, even when the underlying circuit ideas may not qualify for a patent.
By the late 1980s, US and Japanese chip makers were facing rampant “chip piracy”. It allowed competitors to copy layout by reverse-engineering without bearing R& D costs. As a result, US came up with sui generis US Semiconductor Chip Protection Act, 1984. Eventually in 1995, Articles 35–38 TRIPS required the WTO member countries to protect layout design. India’s SICLD Act emerges from this trajectory, creating a separate regime with its own originality standard, registration system, and 10-year term of protection.
The “Forgotten Statute”
For years after the Act was passed, hardly any layout‑design registrations were filed in India, and the key operative sections in fact came into force only around 2011. Prior to October 2014, the Registry had received no applications at all, and that only two certificates have been issued to ISRO and Bharat Electronics Ltd. despite India’s large chip‑design workforce.
Why the Dormancy Matters
It might be tempting to shrug and say: if the industry does not use this law, perhaps that just proves the market does not need it. But in the semiconductor and AI‑hardware context, the invisibility of a dedicated layout regime has deeper implications. It reflects broader patterns in India’s IP and technology governance.
1. Law‑making without lifecycle planning
The layout‑design Act shows how India often treats legislation as a one‑off compliance event rather than as the start of an institutional lifecycle. There was serious engagement at the drafting stage drawing on the Washington Treaty, TRIPS, and comparative models but little evidence of sustained investment in the Registry, periodic amendment, or data‑driven reviews once the law was in force.
The result is a statute that still looks formally “modern,” but has not been tuned to contemporary realities like fabless business models, AI accelerators, or integrated design‑manufacturing consortia.
2. Institutional fragmentation
The IP office’s semiconductor layout‑design page speaks of objectives like “protecting the intellectual property of semiconductor integrated circuits” and “creating awareness,” but those institutional messages appear to operate in a silo, separate from MeitY’s India Semiconductor Mission or the DLI scheme.
There is no obvious mechanism by which, say, a startup receiving design‑linked incentives is nudged towards layout‑design registration, or by which the Registry is looped into policy conversations about AI hardware or open‑source chip initiatives. This kind of fragmentation is not unique to semiconductors, but the stakes here are unusually high.
3. The hierarchy of IP subjects
Legal education and practice in India still privilege a trinity of IP subjects—patents, trademarks, and copyright—with designs, plant varieties, geographical indications, and layout‑designs often treated as peripheral. That hierarchy then feeds into where research funding goes, which statutes young lawyers read, and which areas agencies feel pressured to improve. The SICLD Act sits low on that ladder. Its dormancy is both a symptom and a cause of that ranking.
Conclusion: Can a “Forgotten” Chip Statute Matter in the Age of AI?
The real question is not whether the SICLD Act is “successful” in narrow utilisation terms. Given the registration and litigation data, we already know it is not. The question is what its neglect tells us about whether India’s legal and policy ecosystem has meaningfully integrated semiconductor‑specific IP thinking into its wider technology governance project.
India is investing heavily in fabs, packaging, and design incentives. It is positioning itself as a key node in AI hardware and digital infrastructure and it is increasingly alive to the geopolitical stakes of chip supply chains. Yet the only statute tailored specifically to chip layouts, one that could force richer debate about reverse engineering, incremental innovation, and competitive structure remains largely invisible in practice and in policy. That does not mean the Act, as drafted, is ready to be dusted off and used as‑is.
As AI chips, domain‑specific accelerators, and custom SoCs become the backbone of everything from data centres to defence platforms, the layout of transistors on a die will matter just as much as the abstract ideas in a patent claim. Whether India chooses to treat that layout‑level creativity as a serious object of legal and policy design or leaves it to slumber as a forgotten compliance statute will say a great deal about how deeply it is thinking about sovereignty in the age of silicon.
References
Radhika Aggarwal, “Integrating the Law Behind Integrated Circuits in India”, NLUA Journal of Intellectual Property Rights
Sakshi Bagdi & Abhinav Sharma, “Semiconductor Integrated Circuit Layout Design Protection: Analysis”, International Journal of Legal Science and Innovation (2024)
Kyntiewlin Pakyntein & Dr. Ravi Kant Mishra, “The Semiconductor Layout Design Act, 2000: Filling the IPR Gap in India’s Technology Regime”, International Journal of Law Management & Humanities (2025)
Saurabh Bindal, “The Semiconductor Integrated Circuit Layout Design Act 2000 in India and the mischief of freedom of infringement”, Journal of Intellectual Property Law & Practice (2015)
